计算机系统组成与体系结构 英文版【2025|PDF|Epub|mobi|kindle电子书版本百度云盘下载】

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PARI 1 DiqilAt LOqic ANd FiNiv SIAIE MAChiNfs3

CHAPTER 1 DIGITAL LOGIC FUNDAMENTALS3

1．1 Boolean Algebra4

1．1．1 Basic Functions4

1．1．2 Manipulating Boolean FUnctions6

1．2 Basic Combinatorial Logic13

1．3 More Complex Combinatorial Components16

1．3．1 Multiplexers16

1．3．2 Decoders18

1．3．3 Encoders20

1．3．4 comparators20

1．3．5 Adders and subtracters23

1．3．6 Memory27

1．4 Combinatorial Circuit Designs29

1．4．1 BCD to 7-segment Decoder30

1．4．2 Data Sorter31

PRACIiCAL PERSPECTiVE:WHy LED S ARE USUAllY ACTiVE LOW32

1．5 Basic Sequential Components34

1．6 More Complex Sequential Components39

1．6．1 Counters39

1．6．2 Shift Registers41

1．7 REAl WORld EXAMPlE:PROGRAMMAblE LOqicDEViCES43

1．8 Summary46

Prlblems47

CHAPTER 2 INTRODUCTION TO FINITE STATE MACHINES51

2．1 State Diagrams and State Tables52

HisToRiCAl PERSPECTiVE: FINiTE STATE MACHiNE ANd MiCROPROCESSORS53

2．2 Mealy and Moore Machines56

2．3 Designning State Diagrams58

2．3．1 Modulo 6 Counter58

2．3．2 String Checker60

2．3．3 Toll Booth Controller61

PRACTiCAl PERSPECTiVE: DiffERENT MODElS FOR THE SAME PROblEM157

2．4 From State Diagram to Implementation66

2．4．1 Assigning State Valuse66

2．4．2 Mealy and Moore Machine Implementations68

2．4．3 Generating the Next State70

2．4．4 Generating System Outputs74

2．4．5 An Alternative Desian77

2．4．6 The Eight-State String Checker80

2．5 REAL WORLd EXAMPLE:PRACTiCAL CONSidERATiONS83

2．5．1 Unused States83

2．5．2 Asynchronous Desins86

2．5．3 Machine Conversion91

2．6 Summary92

Problems93

PART 2 COMDUTLR ORGANiZAIiON ANd ARChi ECTURE103

CHAPTER 3 INSTRUCTION SET ARCHITECTURES103

3．1 Levels of Programming Languages104

3．1．1 Language Categories105

3．1．2 Compliling and Asscmbling Programs106

PRACTiCAL PERSPECTiVE: JAVA APPLETS -A DiffERENT WAy of PROCESSiNG PROqRAMS109

3．2 Assembly Language Instructions110

3．2．1 Instruction Types110

3．2．2 Data TyPes112

3．2．3 Addressing Modes113

3．2．4 Instruction Formats115

3．3 Instruction Set Architecture Design119

3．4 A Relatively Simple Instruction Set Architccture121

3．5 REAL WORLd EXAMPLE:THE 8085 MiCROPROCESSOR INSTRUCTiON SET ARCHiTECTURE128

3．5．1 The 8085 Microprocessor Register Set128

HisToRicAl PERSPEcivE:INTEl s EARlyMicRoPRocESSORS129

3．5．2 The 8085 Microprocessor Instruction Set130

3．5．3 A Simple 8085 Program134

3．5．4 Analyzing the 8085 Instruction Set Architecture136

3．6 Summary137

Problems138

CHAPTER 4 INTRODUCTION TO COMPUTER ORGANIZATION141

4．1 Basic Computer Organization142

4．1．1 System Buses142

4．1．2 Instruction Cycles143

PRACTiCAl PERSPECTiVE:THE PERiPHERAl COMPONENT INTERCONNECT BUS144

4．2 CPU Organization146

4．3 Memory Subsystem Organization and Interfacing148

4．3．1 Types of Memory149

4．3．2 Internal Chip Organization151

4．3．3 Memory Subsystem Configuration152

HiSTORiCAl PERSPECTiVE:THE VON NEUMANN ANd HARVARd ARCHiTECTURES157

4．3．4 Multibyte Data Organization157

4．3．5 Beyond the Basics158

4．4 I/O Subsystem Organization and Interfacing159

4．5 A Relatively Simple Computer162

4．6 REAl WORld EXAMPlE:AN 8085-bASEd COMPUTER166

HiSTORiCAl PERSPECTiVE:THE SOjOURNER ROVER170

4．7 Summary171

Problems172

CHAPTER 5 REGISTER TRANSFER LANGUAGES175

5．1 Micro-Operations and Register Transfer Language176

5．2 Using RTL to Specify Digital Systems184

5．2．1 Specification of Digital Components185

5．2．2 Specification and Implementation of Simple Systems186

5．3 More Complex Digital Systems and RTL190

5．3．1 Modulo 6 Counter190

5．3．2 Toll Booth Controller192

5．4 REAL WORld EXAMPlE:VHDL-VHSIC HARdWARE DESCRiPTiON LANqUAGE199

PRACTICAL PERSPECTIVE:HARdWARE DESCRiPTiON LANGUAGES200

5．4．1 VHDL Syntac200

5．4．2 VHDL Design with a High Level of Abstraction203

5．4．3 VHDL Design with a Low Level of Abstraction207

5．5 Summary209

PRACTiCAl PERSPECTiVE: SOME AdVANCEd CAPAbiliTiES of VHDL210

Problems211

CHAPTER 6 CPU DESIGN214

6．1 Specifying a CPU214

6．2 Design and Implementation of a Very Simple CPU216

6．2．1 Specifications for a Very Simple CPU216

6．2．2 Fetching Instructions from Memory217

PRACTiCAL PERSPECTiVE: WHY A CPU INCREMENTS PC DURiNG THE FETCH CyClE218

6．2．3 Decoding Instructions219

6．2．4 Executing Instructions219

6．2．5 Establishing Required Data Paths221

6．2．6 Design of a Very Simple ALU226

6．2．7 Designing the Control Unit Using Hardwired Control227

6．2．8 Design Verification232

6．3 Design and Implementation of a Relatively Simple CPU233

6．3．1 Specifications for a Relatively Simple CPU234

6．3．2 Fetching and Decoding Instructions236

6．3．3 Executing Instructions237

6．3．4 Establishing Data Paths242

6．3．5 Design of a Relatively Simple ALU245

6．3．6 Designing the Control Unit Using Hardwired Control247

6．3．7 Design Verification250

6．4 Shortcomings of the Simple CPUs251

6．4．1 More Internal Registers and Cache251

HisTORiCAl PERSPECTiVE:STORAGE in LNTEl MiCROPROCESSORS252

6．4．2 Multiple Buses Within the CPU253

6．4．3 Pipelined Instruction Processing253

6．4．4 Larger Instruction Sets253

6．4．5 Subroutines and Interrupts256

6．5 REAl WORld EXAMPlE:INTERNAl ARCHiTECTURE of THE 8085 MiCROPROCESSOR256

6．6 Summary256

Problems259

CHAPTER 7 MICROSEQUENCER CONTROL UNIT DESIGN267

7．1 Basic Microsequencer Design268

7．1．1 Microsequencer Operations268

7．1．2 Microinstruction Formats270

7．2 Design and Implementation of a Very Simple Microsequencer272

7．2．1 The Basic Layout272

7．2．2 Generating the Correct Sequence and Designing the Mapping Logic273

7．2．3 Generating the Micro-Operations Using Horizontal Microcode275

7．2．4 Generating the Micro-Operations Using Vertical Microcode277

PRACTiCAL PERSPECTiVE:NANOiNSTRUCTiONS282

7．2．5 Directly Generating the Control Signals from the Microcode283

7．3 Design and Implementation of a Relatively Simple Microsequencer285

7．3．1 Modifying the State Diagram285

7．3．2 Designing the Sequencing Hardware and Microcode285

7．3．3 Completing the Design Using Horizontal Microcode291

7．4 Reducing the Number of Microinstructions294

7．4．1 Microsubroutines294

7．4．2 Microcode Jumps298

7．5 Microprogrammed Control v5. Hardwired Control300

7．5．1 Complexity of the Instruction Set300

7．5．2 Ease of Modification301

7．5．3 Clock Speed301

7．6 REAl WORld EXAMPlE:A (MosTly)MicROCOdEd CPU:THE PENTiUM PROCESSOR301

HiSTORiCAL PERSPECTiVE:HOW THE PENTiUM GOT LTS NAME303

7．7 Summary304

Problems304

CHAPTER 8 COMPUTER ARITHMETIC308

8．1 Unsigned Notation309

8．1．1 Addition and Subtractlon310

8．1．2 Multiplication314

8．1．3 Division323

8．2 Signed Notation334

8．2．1 Signed-Magnitude Notation334

8．2．2 Signed-Two s Complement Notation339

8．3 Binary Coded Decimal340

8．3．1 BCD Numeric Format341

8．3．2 Addition and Subtraction341

8．3．3 Multiplication and Division344

8．4 Specialized Arithmetic Hardware348

HisToRiCAl PERSPECTiVE:COPROCESSORS348

8．4．1 PiPelining349

8．4．2 Lookup Tables351

HiSTORiCAl PERSPECTiVE:THE PENTiUM FlOATiNG POiNT BUG352

8．4．3 Wallace Trees353

8．5 Floating Point Numbers358

8．5．1 Numeric Format358

8．5．2 Numeric Characteristics359

8．5．3 Addition and Subtraction361

8．5．4 Multiplication and Division366

8．6 REAl WORld EXAMPLE:THE IEEE754 FlOATiNG POiNT STANdARd369

8．6．1 Formats369

8．6．2 Denormalized Values371

8．7 Summary371

Problems372

CHAPTER 9 MEMORY ORGANIZATION376

9．1 Hierarchical Memory Systems376

9．2 Cache Memory378

9．2．1 Associative Memory378

9．2．2 Cache Memory with Associative Mapping380

9．2．3 Cache Memory with Direct Mapping383

9．2．4 Cache Memory with Set-Associative Mapping385

PRACTiCAl PERSPECTiVE:MAPPiNG STRATEGiES iN CURRENT CPUS387

9．2．5 Replacing Data in the Cache388

9．2．6 Writing Data to the Cache390

9．2．7 Cache Performance391

9．3 Virtual Memory396

9．3．1 Paging396

9．3．2 Segmentation405

9．3．3 Memory Protection408

9．4 Beyond the Basics of Cache and Virtual Memory410

9．4．1 Beyond the Basics of Cache Memory410

PRACTiCAl PERSPECTiVE:CACHE HiERARCHY in THE lTANIUM MiCROPROCESSOR411

9．4．2 Beyond the Basics of Virtual Memory411

9．5 REAL WORld EXAMPlE:MEMORY MANAGEMENT in A PENTiUM/WiNdOWS PERSONAl COMPUTER413

9．6 Summary414

Problems415

CHAPTER 10 INPUT/OUTPUT ORGANIZATION422

10．1 Asynchronous Data Transfers422

10．1．1 Source-Initiated Data Transfer423

10．1．2 Destination-Initiated Data Transfer425

10．1．3 Handshaking427

10．2 Programmed l/o430

10．2．1 New Instructions434

10．2．2 New Control Signais435

10．2．3 New States and RTL Code435

10．2．4 Modify the CPU Hardware for the New Instruction435

10．2．5 Make Sure Other Instructions Still Work437

10．3 Interrupts438

10．3．1 Transferring Data Between the CPU and I/o Devices438

10．3．2 Types of Interrupts440

10．3．3 Processing Interruptw441

10．3．4 Interrupt Hardware and Priority443

10．3．5 Implementing Interrupts Inside the CPU449

10．4 Direct Memory Access452

10．4．1 Incorporating Direct Memory Access(DMA)into a Computer System452

10．4．2 DMA Transfer Mooes455

10．4．3 Modifying the CPU to Work with DMA456

10．5 I/O Processors458

PRACTiCAl PERSPECTiVE:THE i960I/O PROCESSOR WiTH BUilT/iN DMA461

10．6 Serial Communication462

10．6．1 Serial Communication Basics462

10．6．2 Universal Asynchronous Receiver/Transmitters(UARTs)466

10．7 REAl WORld EXAMPlE:SERLAl COMMUNiCATiON STANdARdS467

10．7．1 The Rs-232-C Standard468

PRACTiCAi PERSPECTiVE:THE RS/422 SERiAl STANdARd469

10．7．2 The Universal Serial Bus Standard470

10．8 Summary471

Problems472

PARI 3 AdvANCFd Topics479

CHAPTER 11 REDUCED INSTRUCTION SET COMPUTING479

11．1 RISC Rationale479

11．1．1 Fixed Length Instructions481

11．1．2 Limited Loading and Storing Instructions Access Memory481

11．1．3 Fewer Addressing Mooes481

11．1．4 Instruction Pipeline481

PRACTiCAl PERSPECTiVE: AddRESSiNG MOdES iN THE POWERPC750 RISC CPU482

11．1．5 Large Number of Registers482

11．1．6 Hardwired Control Unit482

11．1．7 Delayed Loads and Branches482

11．1．8 Speculative Execution of Instructions483

11．1．9 Optimizing Compiler483

11．1．10 Sepqrater Instruction and Data Streams483

11．2 RISC Instruction Sets483

11．3 Instruction Pipelines and Register Windows486

11．3．1 Instruction Pipelines487

11．3．2 Register Windowing and Renaming491

PRACTiCAl PERSPECTiVE: REGiSTER WiNdOWiNG ANd REGiSTER RENAMiNG iN REAl/WORld CPUs494

11．4 Instruction Pipeline Conflicts494

11．4．1 Data Conflicts495

11．4．2 Branch Conflicts498

11．5 RISC vs. CISC504

11．6 REAl WORld EXAMPlE:THE ITANIUM MiCROPROCESSOR506

11．7 Summary509

Problems509

CHAPTER 12 INTRODUCTION TO PARALLEL PROCESSING514

12．1 Parallelism in Uniprocessor Systems515

12．2 Organization of Multiprocessor Systems519

12．2．1 Flynn s Classification519

12．2．2 System Topologies521

12．2．3 MIMD System Architectures524

PRACTiCAl PERSPECTiVE:THE WORld s LARGEST MUlTiCOMPUTER?526

PRACTiCAl PERSPECTiVE:THE BlVE GENE COMPUTER527

12．3 Communication in Multiprocessor Systems528

12．3．1 Fixed Connections528

12．3．2 Reconfigurable Connections529

12．3．3 Routing on Multistage Interconnection Networks534

12．4 Memory Organization in Multiprocessor Systems540

12．4．1 Shared Memory540

12．4．2 Cache Coherence542

12．5 Multiprocessor Operating Systems and Software547

12．6 Parallel Algorithms549

12．6．1 Parallel Bubble Sort549

12．6．2 Parallel Matrix Multiplication551

12．7 Alternative Parallel Architectures554

12．7．1 Dataflow Computing555

12．7．2 Systolic Arrays559

12．7．3 Neural Networks562

12．8 Summary564

Problems564

INDEX569