3维超大规模集成电路 2.5集成方案【2025|PDF|Epub|mobi|kindle电子书版本百度云盘下载】

3维超大规模集成电路 2.5集成方案PDF格式电子书版下载

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1 Introduction1

1.1 2.5-D Integration5

1.2 Enabling Technologies8

1.2.1 Fabrication Technology8

1.2.2 Testing Methodology and Fault Tolerance Technique9

1.2.3 Design Technology10

1.3 Objectives and Book Organization13

References16

2 A Cost Comparison of VLSI Integration Schemes21

2.1 Non-Monolithic Integration Schemes22

2.1.1 Multiple-Reticle Wafer23

2.1.2 Multiple Chip Module(MCM)23

2.1.3 Three-Dimensional(3-D)integration24

2.2 Yield Analysis of Different VLSI Integration Approaches26

2.2.1 Monolithic Soc28

2.2.2 Multiple-Reticle Wafer(MRW)28

2.2.3 Three-Dimensional(3-D)Integration30

2.2.4 2.5-D System Integration31

2.2.5 Multi-Chip Module34

2.2.6 Summing Up35

2.3 Observations37

References38

3 Design Case Studies42

3.1 Crossbar43

3.2 A 2.5-D Rambus DRAM Architecture46

3.2.1 Tackle the Long Bus Wire46

3.2 2 Serialized Channel in the 3rd Dimension48

3.3 A 2.5-D Redesign of PipeRench50

3.3.1 The 2.5-D Implementation52

3.3.2 Simulation Results54

3.4 A 2.5-D Integrated Microprocessor System56

3.4.1 A 2.5-D Integrated Microprocessor System57

3.4.2 An Analytical Performance Model62

3.4.3 Detailed Performance Simulation for Reduced Memory Latency66

3.5 Observations69

References71

4 An Automatic 2.5-D Layout Design Flow74

4.1 A 2.5-D Layout Design Framework75

4.1.1 2.5-D Floorplanning77

4.1.2 2.5-D Placement78

4.1.3 2.5-D Global Routing78

4.2 Observations81

References81

5 Floorplanning for 2.5-D Integration83

5.1 Floorplan Level Evaluation—Category 2 Circuits87

5.1.1 Technique87

5.1.2 Results89

5.2 Floorplan Level Evaluation—Category 3 Circuits91

5.2.1 Technique91

5.2.2 Results92

5.3 Thermal driven floorplanning93

5.3.1 Chip Level Thermal Modeling and Analysis for 2.5-D Floorplanning95

5.3.2 Coupled Temperature and Leakage Estimation99

5.3.3 2.5-D Thermal Driven Floorplanning Techniques105

5.3.4 Experimental results107

5.4 Observations111

References113

6 Placement for 2.5-D Integration117

6.1 Pure Standard Cell Designs119

6.1.1 Placement Techniques120

6.1.2 Benchmarks and Layout Model123

6.1.3 Evaluation of Vertical Partitioning Strategies125

6.1.4 Wire length scaling126

6.1.5 Wire length reduction129

6.1.6 Wire Length vs.Inter-Chip Contact Pitch133

6.2 Mixed Macro and Standard Cell Designs134

6.2.1 Placement Techniques136

6.2.2 Results and Analysis138

6.3 Observations140

References142

7 A Road map of 2.5-D Integration144

7.1 Stacked Memory145

7.2 DRAM Integration for Bandwidth-Demanding Applications147

7.3 Hybrid System Integration151

7.4 Extremely High Performance Systems155

7.4.1 Highly Integrated Image Sensor System155

7.4.2 Radar-in-Cube158

References160

8 Conclusion and Future Work164

8.1 Main Contributions and Conclusions165

8.2 Future Work168

8.2.1 Fabrication Technology for 2.5-D Systems169

8.2.2 Testing Techniques for 2.5-D Integration171

8.2.3 Design Technology for 2.5-D Integration173

References186

Index188

Figure 1.1 Actual chip complexity increases faster than Moore's law2

Figure 1.2 An imaginary 2.5-D system(see colour plate)5

Figure 2.1 Total consumed silicon area of multiple-reticle wafer30

Figure 2.2 Silicon area of the 2.5-D implementation with 4 slices of chips33

Figure 2.3 Silicon area of the 2.5-D implementation34

Figure 2.4 Silicon area of the MCM implementation35

Figure 2.5 Silicon area comparison of different integration schemes36

Figure 2.6 System planning for future VLSI systems38

Figure 3.1 Stick diagram of a monolithic crossbar(see colour plate)44

Figure 3.2 Stick diagram of a 2.5-D crossbar(see colour plate)45

Figure 3.3 Rambus DRAM46

Figure 3.4 2.5-D Rambus DRAM48

Figure 3.5 RDRAM memory system49

Figure 3.6 3-D Rambus DRAM:4-channel configuration50

Figure 3.7 Original monolithic implementation of PipeRench51

Figure 3.8 Critical path of PipeRench system52

Figure 3.9 The 2.5-D re-design of PipeRench(see colourplate)53

Figure 3.10 Alpha 21364 floorplan and memory bus placement58

Figure 3.11 A 2.5-D stacked microprocessor and DRAM60

Figure 3.12 A diagram of computer system60

Figure 3.13 CPI calculation63

Figure 3.14 CPI with regard to main memory latency and L2 cache miss rate(see colour plate)65

Figure 3.15 IPC Speedup by reduced memory latency68

Figure 4.1 A 2.5-D layout synthesis framework76

Figure 4.2 2.5-D routing graph79

Figure 5.1 2.5-D floorplanning87

Figure 5.2 A floorplan example89

Figure 5.3 Insert a 0-weight cell91

Figure 5.4 2.5-D thermal-driven floorplanning flow95

Figure 5.5 A 3-D IC with two stacked chip layers in a package96

Figure 5.6 Thermal interactions between a region of the top transistor layer to all other regions on both transistor layers(not all interactions are drawn)98

Figure 5.7 Thermal simulation of a set of floorplans with varying total area and aspect ratio(only one stacked layer is shown for each case)99

Figure 5.8 Modeling the temperature dependency of the leakage power using a linear model101

Figure 5.9 Leakage power distribution is confined within the placed circuit blocks103

Figure 5.10 The distribution of wire length and temperature gradient109

Figure 5.11 Temperature snapshots of the thermal driven floorplanning with Benchmark AMI49.Both the maximum temperature and the temperature gradient are reduced during the optimization(see colour plate)111

Figure 6.1 2.5-D placement problem(see colour plate)119

Figure 6.2 2.5-D placement process121

Figure 6.3 Wire length reductions vs.vertical partitioning126

Figure 6.4 Monolithic and 2.5-D placements for the same design127

Figure 6.5 A profile of wire length reduction128

Figure 6.6 Wire length reductions of standard cell placement130

Figure 6.7 Wire length distribution of one design132

Figure 6.8 Interconnect power comparison—2-D and 2.5-D solutions133

Figure 6.9 Wire length vs.pitch of inter-chip contact pitch134

Figure 6.10 Block splitting during mixed placement138

Figure 6.11 Wire length reductions of mixed placement140

Figure 7.1 Road map for the development of 2.5-D ICs145

Figure 7.2 Flash memory capacity in cellular phones(adapted from)146

Figure 7.3 Peak memory bandwidths of major NVidia GPUs148

Figure 7.4 Intel's wire-bonded stacked Chip Scale Packaged flash memory(courtesy of Intel Corporation)148

Figure 7.5 Normalized clock rate vs.peak memory bandwidth of NVidia149

Figure 7.6 Tile-based multiprocessor architecture151

Figure 7.7 A multi-chip wireless handset solution(courtesy of Texas Instruments)152

Figure 7.8 Passive components in package155

Figure 7.9 An image sensor system digram156

Figure 7.10 A 2.5-D camera/IR sensor system158

Figure 7.11 Computational demands for military radar systems(adapted from)159

Figure 7.12 Block diagram of a radar system159

Figure 7.13 2.5-D implementation of a radar system160

Figure 8.1 Area power I/O for 2.5-D integration(see colour plate)168

Figure 8.2 MEMS based inter-chip contact(see colour plate)170

Figure 8.3 Design flow for 2.5-D ICs184

Table 1.1 Design variables involved in designing a 2.5-D system11

Table 2.1 Wafer bonding based 3-D integration technologies25

Table 2.2 Values for the major parameters of our cost model28

Table 3.1 SPICE simulation on the critical path55

Table 3.2 Configuration of target microprocessor58

Table 3.3 SPEC2000 benchmark programs under study67

Table 3.4 IPC improvement by Reduced Memory Latency68

Table 5.1 2-D and 2.5-D floorplans for Category 2 designs90

Table 5.2 2-D and 2.5-D floorplans for Category 3 designs93

Table 5.3 2.5-D thermal-driven floorplans with different weighting factors for thermal cost108

Table 5.4 3-D floorplans with and without thermal concern110

Table 6.1 Placement benchmarks123

Table 6.2 Worst-case wire length reduction for nets with large fan-out129

Table 6.3 Wire length comparison of standard cell placements131

Table 6.4 Mixed Layout Benchmarks135

Table 6.5 Wire length characteristics of mixed placement139