Digital Design With RTL Design【2025|PDF|Epub|mobi|kindle电子书版本百度云盘下载】

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CHAPTER 1 Introduction1

1.1 Digital Systems in the World Around Us1

1.2 The World of Digital Systems4

Digital versus Analog4

Digital Encodings and Binary Numbers——0s and 1s9

1.3 Implementing Digital Systems：Microprocessors versus Digital Circuits22

Software on Microprocessors：The Digital Workhorse22

Digital Design——When Microprocessors Aren’t Good Enough26

1.4 About this Book28

1.5 Exercises29

CHAPTER 2 Combinational Logic Design35

2.1 Introduction35

2.2 Switches36

Electronics 10136

The Amazing Shrinking Switch37

2.3 The CMOS Transistor40

2.4 Boolean Logic Gates——Building Blocks for Digital Circuits43

Boolean Algebra and its Relation to Digital Circuits43

AND，OR，＆ NOT Gates46

Building Simple Circuits Using Gates49

2.5 Boolean Algebra52

Notation and Terminology53

Some Properties of Boolean Algebra55

Complementing a Function60

2.6 Representations of Boolean Functions61

Equations62

Circuits62

Truth Tables62

Converting among Boolean Function Representations64

Standard Representation and Canonical Form68

Multiple-Output Combinational Circuits71

2.7 Combinational Logic Design Process73

2.8 More Gates80

NAND＆NOR80

XOR＆XNOR81

Interesting Uses of these Additional Gates82

Completeness of NAND and of NOR82

Number of Possible Logic Gates83

2.9 Decoders and Muxes84

Decoders84

Multiplexers（Muxes）86

2.10 Additional Considerations91

Nonideal Gate Behavior——Delay91

Active Low Inputs92

Demultiplexers and Encoders93

Schematic Capture and Simulation93

2.11 Combinational Logic Optimizations and Tradeoffs（See Section 6.2）95

2.12 Combinational Logic Description UsingHardware Description Languages（See Section 9.2）95

2.13 Chapter Summary96

2.14 Exercises96

CHAPTER 3 Sequential Logic Design：Controllers105

3.1 Introduction105

3.2 Storing One Bit——Flip-Flops106

Feedback——The Basic Storage Method106

Basic SR Latch107

Level -Sensitive SR Latch111

Level-Sensitive D Latch——A Basic Bit Store112

Edge-Triggered D Flip-Flop——A Robust Bit Store113

Clocks and Synchronous Circuits117

Basic Register——Storing Multiple Bits120

3.3 Finite-State Machines（FSMs）122

Mathematical Formalism for Sequential Behavior——FSMs124

How to Capture Desired System Behavior as an FSM129

3.4 Controller Design132

Standard Controller Architecture for Implementing an FSM as a Sequential Circuit132

Controller（Sequential Logic）Design Process133

Converting a Circuit to an FSM（Reverse Engineering）140

Common Mistakes when Capturing FSMs142

FSM and Controller Conventions145

3.5 More on Flip-Flops and Controllers146

Non-Ideal Flip-Flop Behavior146

Flip-Flop Reset and Set Inputs149

Initial State of a Controller150

Non-Ideal Controller Behavior：Output Glitches151

3.6 Sequential Logic Optimizations and Tradeoffs（See Section 6.3）153

3.7 Sequential Logic Description Using Hardware Description Languages（See Section 9.3）153

3.8 Product Profile——Pacemaker153

3.9 Chapter Summary156

3.10 Exercises157

CHAPTER 4 Datapath Components167

4.1 Introduction167

4.2 Registers168

Parallel-Load Register168

Shift Register173

Multifunction Registers175

Register Design Process179

4.3 Adders181

Adder——Carry-Ripple Style183

4.4 Comparators191

Equality（Identity）Comparator191

Magnitude Comparator——Carry-Ripple Style192

4.5 Multiplier——Array-Style195

4.6 Subtractors and Signed Numbers196

Subtractor for Positive Numbers Only196

Representing Negative Numbers：Two’s Complement Representation200

Building a Subtractor Using an Adder and Two’s Complement203

Detecting Overflow205

4.7 Arithmetic-Logic Units——ALUs207

4.8 Shifters210

Simple Shifters211

Barrel Shifter214

4.9 Counters and Timers215

Up-Counter216

Up/Down-Counter217

Counter with Load218

Timers222

4.10 Register Files225

4.11 Datapath Component Tradeoffs（See Section 6.4）230

4.12 Datapath Component Description Using Hardware Description Languages（See Section 9.4）230

4.13 Product Profile：An Ultrasound Machine230

Functional Overview231

Digital Circuits in an Ultrasound Machine’s Beamformer234

Future Challenges in Ultrasound237

4.14 Chapter Summary237

4.15 Exercises238

CHAPTER 5 Register-Transfer Level（RTL）Design247

5.1 Introduction247

5.2 High-Level State Machines248

5.3 RTL Design Process255

Step 2A——Greating a Datapath using Components from a Library259

Step 2BConnecting the Datapath to a Controller262

Step 2C——Deriving the Controller’s FSM263

5.4 More RTL Design264

Additional Datapath Components for the Library264

RTL Design Involving Register Files or Memories265

RTL Design Pitfall Involving Storage Updates271

RTL Design Involving a Timer272

A Data-Dominated RTL Design Example275

5.5 Determining Clock Frequency278

5.6 Behavioral-Level Design：C to Gates（Optional）281

5.7 Memory Components285

Random Access Memory（RAM）286

Bit Storage in a RAM288

Using a RAM290

Read-Only Memory（ROM）292

ROM Types294

Using a ROM297

The Blurring of the Distinction between RAM and ROM299

5.8 Queues（FIFOs）299

5.9 Multiple Processors303

5.10 Hierarchy——A Key Design Concept305

Managing Complexity305

Abstraction306

Composing a Larger Component from Smaller Versions of the Same Component307

5.11 RTL Design Optimizations and Tradeoffs（See Section 6.5）309

5.12 RTL Design Using Hardware Description Languages（See Section 9.5）310

5.13 Product Profile：Cell Phone310

Cells and Basestations310

How Cellular Phone Calls Work311

Inside a Cell Phone312

5.14 Chapter Summary316

5.15 Exercises317

CHAPTER 6 Optimizations and Tradeoffs325

6.1 Introduction325

6.2 Combinational Logic Optimizations and Tradeoffs327

Two-Level Size Optimization Using Algebraic Methods327

A Visual Method for Two-Level Size Optimization——K-Maps329

Don’t Care Input Combinations336

Automating Two-Level Logic Size Optimization339

Multilevel Logic Optimization——Performance and Size Tradeoffs348

6.3 Sequential Logic Optimizations and Tradeoffs351

State Reduction351

State Encoding354

Moore versus Mealy FSMs360

6.4 Datapath Component Tradeoffs365

Faster Adders365

Smaller Multiplier——Sequential（Shift-and-Add）Style375

6.5 RTL Design Optimizations and Tradeoffs377

Pipelining377

Concurrency380

Component Allocation381

Operator Binding382

Operator Scheduling383

Moore versus Mealy High-Level State Machines386

6.6 More on Optimizations and Tradeoffs386

Serial versus Concurrent Computation386

Optimizations and Tradeoffs at Higher versus Lower Levels of Design387

Algorithm Selection388

Power Optimization389

6.7 Product Profile：Digital Video Player/Recorder393

Digital Video Overview393

DVD——One Form of Digital Video Storage393

MPEG-2 Video Encoding——Sending Frame Differences Using I-，P-，and B-Frames395

Transforming to the Frequency Domain for Further Compression396

6.8 Chapter Summary402

6.9 Exercises403

CHAPTER 7 Physical Implementation on ICs413

7.1 Introduction413

7.2 Manufactured IC Types414

Full-Custom Integrated Circuits414

Semicustom（Application-Specific）Integrated Circuits——ASICs415

7.3 Off-the-Shelf Programmable IC Type——FPGA423

Lookup Tables424

Mapping a Circuit among Multiple Lookup Tables426

Programmable Interconnects（Switch Matrices）432

Configurable Logic Block434

Overall FPGA Architecture436

7.4 Other Off-the-Shelf IC Types438

Off-the-Shelf Logic（SSI）IC438

Simple Programmable Logic Device（SPLD）441

Complex Programmable Logic Device（CPLD）445

FPGA-to-Structured-ASIC Flows445

7.5 IC Tradeoffs，Trends，and Comparisons446

Tradeoffs Among IC Types447

IC Technology Trend——Moore’s Law448

Relative Popularity of IC Types450

ASSPs450

IC Types versus Processor Varieties451

FPGAs alongside Microprocessors452

7.6 Product Profile：Giant LED-Based Video Display with FPGAs453

7.7 Chapter Summary457

7.8 Exercises457

CHAPTER 8 Programmable Processors461

8.1 Introduction461

8.2 Basic Architecture462

Basic Datapath462

Basic Control Unit465

8.3 A Three-Instruction Programmable Processor469

A First Instruction Set with Three Instructions469

Control Unit and Datapath for the Three-Instruction Processor471

8.4 A Six-Instruction Programmable Processor475

Extending the Instruction Set475

Extending the Control Unit and Datapath476

8.5 Example Assembly and Machine Programs478

8.6 Further Extensions to the Programmable Processor480

Instruction Set Extensions480

Input/Output Extensions481

Performance Extensions481

8.7 Chapter Summary482

8.8 Exercises483

CHAPTER 9 Hardware Description Languages487

9.1 Introduction487

9.2 Combinational Logic Description Using Hardware Description Languages489

Structure489

Combinational Behavior494

Testbenches498

9.3 Sequential Logic Description Using Hardware Description Languages501

Register501

Oscillator503

Controllers505

9.4 Datapath Component Description Using Hardware Description Languages509

Full-Adders509

Carry-Ripple Adders511

Up-Counter514

9.5 RTL Design Using Hardware Description Languages517

High-Level State Machine of the Laser-Based Distance Measurer517

Controller and Datapath of the Laser-Based Distance Measurer523

9.6 Chapter Summary532

9.7 Exercises532

APPENDIX A Boolean Algebras537

A.1 Boolean Algebra537

A.2 Switching Algebra538

A.3 Important Theorems in Boolean Algebra540

A.4 Other Examples of Boolean Algebras545

A.5 Further Readings545

APPENDIX B Additional Topics in Binary Number Sys-tems547

B.1 Introduction547

B.2 Real Number Representation547

B.3 Fixed Point Arithmetic550

B.4 Floating Point Representation551

The IEEE 754-1985 Standard552

B.5 Exercises556

APPENDIX C Extended RTL Design Example557

C.1 Introduction557

C.2 Designing the Soda Dispenser Controller558

C.3 Understanding the Behavior of the Soda Dispenser Controller and Datapath562